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Synopsys | Synopsys hiring for R&D Engineers | Fresher Jobs in Bangalore | FreeJobAlert|Fresher Jobs


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About Synopsys: At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.

Synopsys Fresher Recruitment Details

Company Name: Synopsys

Degree Needed: BE/BTech/ME/MTech

Experience Needed: 0-2 Yrs Job Profile: R&D Engineer

Work Location: Bangalore

Job Description and Requirements

  • We’re looking for an R&D engineer in the ProtoCompiler R&D team in Bangalore for the following role.

  • You would be responsible for designing, developing, troubleshooting, debugging, and maintaining large and efficient software systems for partitioning, logic, timing optimization, technology mapping steps of the FPGA prototyping software.

You would be expected to:

  • Given a requirement or functional specification, design, and implement efficient data structures and algorithms in C/C++.

  • Work with the AE team in test planning, execution, and customer support.

  • Maintain and support existing products and features.

Key Qualifications

You will have:

  • B.Tech/M. Tech in CS/EE from a reputed institute.

  • Sound knowledge in data structures, graph algorithms, and C/C++ programming on Windows/Unix.

  • Familiarity in digital logic design.

  • Familiarity with Verilog/VHDL RTL level designs, timing constraints, static timing analysis

Preferred Experience

  • 0-2 years of experience in designing, developing, and maintaining large EDA software.

  • Working knowledge of FPGA prototyping tools and flows is a plus.

Apply Before the link Expires for Synopsys Fresher Recruitment.

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